An ever present goal in the semiconductor industry has been to decrease the size of devices and to increase the performance of devices. However, both of these goals present large technical hurdles as the two goals are often in conflict with each other.
As the minimum feature size achievable in semiconductor manufacturing decreases, the capacitive coupling between adjacent metal lines becomes a significant impediment to achieving higher performance. Further, as the minimum feature size decreases, the number of devices potentially achievable in a given area increases, as a second power function. The number of wiring connections is increasing at least as rapidly. In order to accommodate the increased wiring, the chip designer would like to shrink the space between adjacent lines to the minimum achievable dimension. This has the unfortunate effect of increasing the capacitive load.
One way to accommodate the increased wiring and reduce capacitive load is to substitute lower dielectric constant materials for the insulating material. A common insulating material to date is SiO2, which has a dielectric constant of around 4. SiO2 is now used in most very large scale integrated circuit (VLSI) chips. Another way to accommodate the increased wiring and reduce capacitive load is to shorten the distance between devices by denser packaging.
Multi-chip stacking has been proposed in the past; however, one significant concern with stacking chips (i.e. memory chips, logic chips, processor chips, etc.) is the manufacturing yield of the assembly. Because any given wafer will currently have a percentage of defective chips on its surface, when multiple wafers are stacked, for example 10 wafers high, the likelihood of at least one defective chip in any given stack goes up significantly. Alternatively, stacking individual chips that have been tested and known to be good involves a greater amount of high precision handling when compared to stacking wafers prior to dicing. In either scenario, a high amount of loss due to manufacturing yield is present.
What are needed are methods and devices that improve the manufacturing yield of large numbers of stacked chips in a multi-chip assembly. What are also needed are improved methods and devices to enhance performance, reduce size, and improve other properties and features of multi-chip assemblies.